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| TUESDAY, June 8, 2004, 10:30 AM - 12:00 PM | Room: 4 |
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TOPIC AREA: SYSTEM-LEVEL DESIGN AND VERIFICATION
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SESSION 5
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| Timing-Driven System Synthesis
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| Chair: Prashant Sawkar - Intel Corp., Hillsboro, OR
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| Organizers: Gila Kamhi, Krzysztof Kuchcinski
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| This session includes papers discussing different approaches to timing-driven modular design. Results are provided on scalable system level design with tight connections to physical level timing requirements. The first two papers promote scalable and hierarchical design methodology through modular scheduling and formal synthesis of timing optimised scheduling algorithms. The last two papers discuss timing problems at the system level in connection to physical design. Their approaches address the problem of handling system level long wire delays encountered at later design stages.
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| 5.1 |
Modular Scheduling of Guarded Atomic Actions
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| Speaker(s): | Daniel L. Rosenband - Massachusetts Institute of Tech., Cambridge, MA
Arvind - Massachusetts Institute of Tech., Cambridge, MA
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| Author(s): | Daniel L. Rosenband - Massachusetts Institute of Tech., Cambridge, MA
Arvind - Massachusetts Institute of Tech., Cambridge, MA
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| 5.2 | Automatic Correct Scheduling of Control Flow Intensive Behavioral Descriptions in Formal Synthesis |
| Speaker(s): | Kai Kapp - Univ. of Karlsruhe, Karlsruhe, Germany
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| Author(s): | Kai Kapp - Univ. of Karlsruhe, Karlsruhe, Germany
Viktor Sabelfeld - Univ. of Karlsruhe, Karlsruhe, Germany
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| 5.3s | A Timing-Driven Chip-Level Design Flow |
| Speaker(s): | Fan Mo - Univ. of California, Berkeley, CA
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| Author(s): | Fan Mo - Univ. of California, Berkeley, CA
Robert K. Brayton - Univ. of California, Berkeley, CA
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| 5.4s | Timing Closure through a Globally Synchronous Timing Partitioned Design Methodology |
| Speaker(s): | Anders Edman - Linkoping Univ., Linkoping, Sweden
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| Author(s): | Anders Edman - Linkoping Univ., Linkoping, Sweden
Christer Svensson - Linkoping Univ., Linkoping, Sweden
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